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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 10:55:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-01 10:55:24 -0700 |
| commit | ef757002dbc8280a65d25618e57b20d3dbadd64a (patch) | |
| tree | c9751dd4fc6383a163e4d6b6a06ed51c2e5eeeaa /passes | |
| parent | 659c04a68d15b20a9421ea5d154b259265f39494 (diff) | |
| download | yosys-ef757002dbc8280a65d25618e57b20d3dbadd64a.tar.gz yosys-ef757002dbc8280a65d25618e57b20d3dbadd64a.tar.bz2 yosys-ef757002dbc8280a65d25618e57b20d3dbadd64a.zip | |
Also remove $__ABC_FF_
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 2eee43739..30df8e3ef 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -566,7 +566,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri vector<RTLIL::Cell*> boxes; for (const auto &it : module->cells_) { auto cell = it.second; - if (cell->type.in("$_AND_", "$_NOT_")) { + if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) { module->remove(cell); continue; } |