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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 15:10:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 15:10:43 -0700 |
| commit | ed7540a46f22151d6c87205df92bc52f5e875130 (patch) | |
| tree | 16845bb791d92c2aec298c76dad7b3aebd29fdd2 /passes | |
| parent | 105aaeaf598a04020fa5030c947f623f0daa38da (diff) | |
| download | yosys-ed7540a46f22151d6c87205df92bc52f5e875130.tar.gz yosys-ed7540a46f22151d6c87205df92bc52f5e875130.tar.bz2 yosys-ed7540a46f22151d6c87205df92bc52f5e875130.zip | |
Pack P register properly
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index d87d63670..be510b4cb 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -86,14 +86,16 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm) else D = st.ffP->getPort("\\D"); SigSpec Q = st.ffP->getPort("\\Q"); - P.replace(D, Q); - cell->setPort("\\P", Q); + P.replace(pm.sigmap(D), Q); + cell->setPort("\\P", P); cell->setParam("\\PREG", State::S1); if (st.ffP->type == "$dff") cell->setPort("\\CEP", State::S1); else if (st.ffP->type == "$dffe") cell->setPort("\\CEP", st.ffP->getPort("\\EN")); else log_abort(); + + st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P))); } log(" clock: %s (%s)", log_signal(st.clock), "posedge"); |