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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 13:06:49 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 13:06:49 -0700 |
| commit | e9eb855d38b3bd4d5a61471af49e791be12817ba (patch) | |
| tree | d62378567e27d99a0536c4cdbea5be6d60e4ffed /passes | |
| parent | d232e6a6cd8ed0ac0e76a1e6b787cb6dead855f0 (diff) | |
| download | yosys-e9eb855d38b3bd4d5a61471af49e791be12817ba.tar.gz yosys-e9eb855d38b3bd4d5a61471af49e791be12817ba.tar.bz2 yosys-e9eb855d38b3bd4d5a61471af49e791be12817ba.zip | |
Make unextend a udata
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 6e726d1c2..6998d6e84 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -1,6 +1,6 @@ pattern xilinx_dsp -state <std::function<SigSpec(const SigSpec&)>> unextend +udata <std::function<SigSpec(const SigSpec&)>> unextend state <SigBit> clock state <SigSpec> sigA sigffAcemuxY sigB sigffBcemuxY sigC sigffCcemuxY sigD sigffDcemuxY sigM sigP state <IdString> postAddAB postAddMuxAB @@ -23,7 +23,7 @@ match dsp select dsp->type.in(\DSP48E1) endmatch -code unextend sigA sigB sigC sigD sigM +code sigA sigB sigC sigD sigM unextend = [](const SigSpec &sig) { int i; for (i = GetSize(sig)-1; i > 0; i--) @@ -396,7 +396,6 @@ endcode subpattern out_dffe arg argD argQ clock -arg unextend code dff = nullptr; |