diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-29 20:14:25 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-29 20:14:25 +0200 |
| commit | e605af8a4937533b35068071e14f5bd92c2e5b4f (patch) | |
| tree | cd7348576a824d40b25a7891f0b3b0b339c49573 /passes | |
| parent | 2145e57ef08784484e875e64cb43b6d1f4dbe50c (diff) | |
| download | yosys-e605af8a4937533b35068071e14f5bd92c2e5b4f.tar.gz yosys-e605af8a4937533b35068071e14f5bd92c2e5b4f.tar.bz2 yosys-e605af8a4937533b35068071e14f5bd92c2e5b4f.zip | |
Fixed Verilog pre-processor for files with no trailing newline
Diffstat (limited to 'passes')
0 files changed, 0 insertions, 0 deletions