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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 12:46:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 12:46:07 -0700 |
| commit | dac5adde12c585f5e0552f776ae0a5ab05e995c9 (patch) | |
| tree | 24c40fe9c6a50c6fc031058fdb3ca0cedad12cbb /passes | |
| parent | 8d3f6d0d792a1cd688ce4d9c05bef8ec601f9334 (diff) | |
| download | yosys-dac5adde12c585f5e0552f776ae0a5ab05e995c9.tar.gz yosys-dac5adde12c585f5e0552f776ae0a5ab05e995c9.tar.bz2 yosys-dac5adde12c585f5e0552f776ae0a5ab05e995c9.zip | |
design: -import to not count black/white-boxes as candidates for top
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/design.cc | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index cfe97067d..421defe0c 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -228,14 +228,20 @@ struct DesignPass : public Pass { } if (import_mode) { + std::vector<RTLIL::Module*> candidates; for (auto module : copy_src_modules) { if (module->get_bool_attribute(ID::top)) { - copy_src_modules.clear(); - copy_src_modules.push_back(module); + candidates.clear(); + candidates.push_back(module); break; } + if (!module->get_blackbox_attribute()) + candidates.push_back(module); } + + if (GetSize(candidates) == 1) + copy_src_modules = std::move(candidates); } } |