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| author | Clifford Wolf <clifford@clifford.at> | 2016-10-25 23:21:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-10-25 23:21:37 +0200 |
| commit | d9d38eeedba7d650ff80e2b364f2f40e9ff1673b (patch) | |
| tree | 7ea160e7d659b240f0e82ede21643b7213197202 /passes | |
| parent | aa7226233023dcd53a28de837de74fb60fa9d691 (diff) | |
| download | yosys-d9d38eeedba7d650ff80e2b364f2f40e9ff1673b.tar.gz yosys-d9d38eeedba7d650ff80e2b364f2f40e9ff1673b.tar.bz2 yosys-d9d38eeedba7d650ff80e2b364f2f40e9ff1673b.zip | |
Bugfix in fsm_map for FSMs without reset state
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/fsm/fsm_map.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 5b32ed599..c42303752 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -272,7 +272,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) } else { - RTLIL::SigSpec sig_a, sig_b, sig_s; + RTLIL::SigSpec sig_a(RTLIL::State::Sx, next_state_wire->width); + RTLIL::SigSpec sig_b, sig_s; int reset_state = fsm_data.reset_state; if (reset_state < 0) reset_state = 0; |