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author | Clifford Wolf <clifford@clifford.at> | 2019-02-24 20:34:23 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-02-24 20:34:23 +0100 |
commit | cd722f26a5437e145c02c49b5736bd03b13927da (patch) | |
tree | 6c27e28e1b6d3648112ca7ee8dd5b8835478ca4a /passes | |
parent | da14bc8524c21c0d33a82fcb66d08d08f2654e6e (diff) | |
download | yosys-cd722f26a5437e145c02c49b5736bd03b13927da.tar.gz yosys-cd722f26a5437e145c02c49b5736bd03b13927da.tar.bz2 yosys-cd722f26a5437e145c02c49b5736bd03b13927da.zip |
Cleanups in ARST handling in wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes')
-rw-r--r-- | passes/opt/wreduce.cc | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index c550b402e..09983bc67 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -196,16 +196,10 @@ struct WreduceWorker work_queue_bits.insert(bit); // Narrow ARST_VALUE parameter to new size. - // - // Note: This works because earlier loop only removes signals from - // the upper bits of the DFF. - if(cell->parameters.count("\\ARST_VALUE") > 0) { - RTLIL::Const old_arst_value = cell->parameters.at("\\ARST_VALUE"); - std::vector<RTLIL::State> new_arst_value(GetSize(sig_q)); - for(int i = 0; i < GetSize(sig_q); ++i) { - new_arst_value[i] = old_arst_value[i]; - } - cell->parameters["\\ARST_VALUE"] = RTLIL::Const(new_arst_value); + if (cell->parameters.count("\\ARST_VALUE")) { + Const arst_value = cell->getParam("\\ARST_VALUE"); + arst_value.bits.resize(GetSize(sig_q)); + cell->setParam("\\ARST_VALUE", arst_value); } cell->setPort("\\D", sig_d); |