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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-31 13:39:30 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-31 13:39:30 +0100 |
| commit | ccdbf41be60f78df9f8f2347026aaaf03693bd35 (patch) | |
| tree | a843b27cacc7a07f60e966f941cbf541bea98c34 /passes | |
| parent | 864808992be407a9b33f222fa5846f5cd5f149ea (diff) | |
| download | yosys-ccdbf41be60f78df9f8f2347026aaaf03693bd35.tar.gz yosys-ccdbf41be60f78df9f8f2347026aaaf03693bd35.tar.bz2 yosys-ccdbf41be60f78df9f8f2347026aaaf03693bd35.zip | |
Improvements in wreduce
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/wreduce.cc | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index df416e4c5..4f08da675 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -201,6 +201,31 @@ struct WreduceWorker if (max_port_b_size >= 0) run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something); + if (cell->hasPort("\\A") && cell->hasPort("\\B") && port_a_signed && port_b_signed) { + SigSpec sig_a = mi.sigmap(cell->getPort("\\A")), sig_b = mi.sigmap(cell->getPort("\\B")); + if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 && + GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) { + log("Converting cell %s.%s (%s) from signed to unsigned.\n", + log_id(module), log_id(cell), log_id(cell->type)); + cell->setParam("\\A_SIGNED", 0); + cell->setParam("\\B_SIGNED", 0); + port_a_signed = false; + port_b_signed = false; + did_something = true; + } + } + + if (cell->hasPort("\\A") && !cell->hasPort("\\B") && port_a_signed) { + SigSpec sig_a = mi.sigmap(cell->getPort("\\A")); + if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) { + log("Converting cell %s.%s (%s) from signed to unsigned.\n", + log_id(module), log_id(cell), log_id(cell->type)); + cell->setParam("\\A_SIGNED", 0); + port_a_signed = false; + did_something = true; + } + } + // Reduce size of port Y based on sizes for A and B and unused bits in Y |