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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 10:40:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | c50601e35e9444e9fb77fd89622b3263d85d1fd0 (patch) | |
| tree | 439451868dfe75e022e7bfbcb9ba41b2782d092e /passes | |
| parent | 8fbb55f4aba9ccb850680dc9c7ab582e8c964a4a (diff) | |
| download | yosys-c50601e35e9444e9fb77fd89622b3263d85d1fd0.tar.gz yosys-c50601e35e9444e9fb77fd89622b3263d85d1fd0.tar.bz2 yosys-c50601e35e9444e9fb77fd89622b3263d85d1fd0.zip | |
abc9: restore selected_modules()
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 976b6462e..4843200d8 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -128,7 +128,7 @@ void prep_dff_hier(RTLIL::Design *design) Design *unmap_design = new Design; - for (auto module : design->modules()) + for (auto module : design->selected_modules()) for (auto cell : module->cells()) { auto inst_module = design->module(cell->type); if (inst_module && inst_module->attributes.count(ID::abc9_flop)) { |