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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 11:19:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 11:19:54 -0700 |
| commit | b89bb744529fc8a5e4cd38522f86a797117f2abc (patch) | |
| tree | f4a796c20ab098bf2884bfabdc2779dab51ff198 /passes | |
| parent | a2b106135b29d1d44255f1b3b6c4173c6e1f3624 (diff) | |
| download | yosys-b89bb744529fc8a5e4cd38522f86a797117f2abc.tar.gz yosys-b89bb744529fc8a5e4cd38522f86a797117f2abc.tar.bz2 yosys-b89bb744529fc8a5e4cd38522f86a797117f2abc.zip | |
For 'stat' do not count modules with abc_box_id
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/stat.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 54f4ea817..3909c4c8c 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -269,6 +269,9 @@ struct StatPass : public Pass { if (mod->get_bool_attribute("\\top")) top_mod = mod; + if (mod->attributes.count("\\abc_box_id")) + continue; + statdata_t data(design, mod, width_mode, cell_area); mod_stat[mod->name] = data; |