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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-11 16:18:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-11 16:18:01 -0700 |
| commit | b15b410b41cca3a79bfcfc9c91f665815f31ab5b (patch) | |
| tree | 52f709e41492cce25ece4b071b54b2572bf4435e /passes | |
| parent | b1f1db2fcf0e27fbd9cb7b94ab5c9d8879ad9694 (diff) | |
| download | yosys-b15b410b41cca3a79bfcfc9c91f665815f31ab5b.tar.gz yosys-b15b410b41cca3a79bfcfc9c91f665815f31ab5b.tar.bz2 yosys-b15b410b41cca3a79bfcfc9c91f665815f31ab5b.zip | |
Remove unused
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/pmux2shiftx.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/passes/techmap/pmux2shiftx.cc b/passes/techmap/pmux2shiftx.cc index 9b05f8f6d..08cb06d5f 100644 --- a/passes/techmap/pmux2shiftx.cc +++ b/passes/techmap/pmux2shiftx.cc @@ -73,7 +73,6 @@ struct Pmux2ShiftxPass : public Pass { pmux_s.append(cell->getPort("\\S")); RTLIL::SigSpec pmux_y = module->addWire(NEW_ID, clog2width); - RTLIL::SigSpec shiftx_s = module->addWire(NEW_ID, 1 << clog2width); module->addPmux(NEW_ID, RTLIL::Const(RTLIL::Sx, clog2width), pmux_b, pmux_s, pmux_y); module->addShiftx(NEW_ID, shiftx_a, pmux_y, cell->getPort("\\Y")); module->remove(cell); |