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| author | Clifford Wolf <clifford@clifford.at> | 2017-01-26 08:59:26 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-01-26 08:59:26 +0100 |
| commit | b0a430f601647894886360d446bf136aac0a72ca (patch) | |
| tree | be396f5e653d3158981aee2a237d1b5d5bbf2bc7 /passes | |
| parent | fea528280b9e598ae13178c9ce4ac16e569c46a8 (diff) | |
| parent | b54972c1120fa6c5f4dc85d58178fb1211547691 (diff) | |
| download | yosys-b0a430f601647894886360d446bf136aac0a72ca.tar.gz yosys-b0a430f601647894886360d446bf136aac0a72ca.tar.bz2 yosys-b0a430f601647894886360d446bf136aac0a72ca.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 337af7fd7..f1c4a1d3b 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -175,16 +175,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check { filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v"; if (check_file_exists(filename)) { - std::vector<std::string> args; - args.push_back(filename); Frontend::frontend_call(design, NULL, filename, "verilog"); goto loaded_module; } filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il"; if (check_file_exists(filename)) { - std::vector<std::string> args; - args.push_back(filename); Frontend::frontend_call(design, NULL, filename, "ilang"); goto loaded_module; } |