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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 20:25:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 20:25:59 -0700 |
| commit | 9f608d6be30c9302c0e3810525457e39f57b0334 (patch) | |
| tree | 29c8a2d03cfd72942265b3d4f1068671539e98e5 /passes | |
| parent | ea6ffea2cd580542cbb5cc349f5268af0700e292 (diff) | |
| download | yosys-9f608d6be30c9302c0e3810525457e39f57b0334.tar.gz yosys-9f608d6be30c9302c0e3810525457e39f57b0334.tar.bz2 yosys-9f608d6be30c9302c0e3810525457e39f57b0334.zip | |
write_verilog with *.v extension
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 6e57ab7f3..330361f65 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -435,7 +435,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // count_gates, GetSize(signal_list), count_input, count_output); #if 0 - Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.xaig", tempdir_name.c_str())); + Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.v", tempdir_name.c_str())); #endif Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str())); |