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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-04 23:00:32 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-04 23:00:32 +0100 |
| commit | 99b9c56da17403152f1bba3ce00c4f34fcb316ce (patch) | |
| tree | 413cc12c8b2381976a073a9d95f3d1b1733dc40b /passes | |
| parent | 69e867f3e820bb52d9dc51dff22ca5ba355393c5 (diff) | |
| download | yosys-99b9c56da17403152f1bba3ce00c4f34fcb316ce.tar.gz yosys-99b9c56da17403152f1bba3ce00c4f34fcb316ce.tar.bz2 yosys-99b9c56da17403152f1bba3ce00c4f34fcb316ce.zip | |
Fixed detection of init attribute in opt_rmdff
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 02b7f77e7..9a438537c 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -73,7 +73,7 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) assign_map.apply(sig_c); assign_map.apply(sig_r); - bool has_init; + bool has_init = false; RTLIL::Const val_init; for (auto bit : dff_init_map(sig_q).to_sigbit_vector()) { if (bit.wire == NULL) |