diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 12:44:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 12:44:10 -0700 |
| commit | 98c297fabfb960beadedaccf7cc9f765f20e044b (patch) | |
| tree | 6d898dc3f29615f1d42bfc562192ffc849dcaa0f /passes | |
| parent | 53b19ab1f5631bcfc6c3def14f5d44ecc05c1cbc (diff) | |
| download | yosys-98c297fabfb960beadedaccf7cc9f765f20e044b.tar.gz yosys-98c297fabfb960beadedaccf7cc9f765f20e044b.tar.bz2 yosys-98c297fabfb960beadedaccf7cc9f765f20e044b.zip | |
ABC to read_box before reading netlist
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index fbf3a47ee..f5f7add9a 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -322,7 +322,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n", module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str()); - std::string abc_script = stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str()); + std::string abc_script; if (!liberty_file.empty()) { abc_script += stringf("read_lib -w %s; ", liberty_file.c_str()); @@ -343,6 +343,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri else abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str()); + abc_script += stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str()); + if (!script_file.empty()) { if (script_file[0] == '+') { for (size_t i = 1; i < script_file.size(); i++) |