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| author | Brett Witherspoon <brett@witherspoondesign.com> | 2021-06-22 09:51:41 -0500 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-08-12 22:41:41 -0600 |
| commit | 979053855c85b72c6344bf6350fb9a8360f3d092 (patch) | |
| tree | ffe80454cbe9dfd862ea93f93124533e38fe4fae /passes | |
| parent | c8023e37d82adffd0c0ba54575c949be9da45198 (diff) | |
| download | yosys-979053855c85b72c6344bf6350fb9a8360f3d092.tar.gz yosys-979053855c85b72c6344bf6350fb9a8360f3d092.tar.bz2 yosys-979053855c85b72c6344bf6350fb9a8360f3d092.zip | |
sv: improve support for wire and var with user-defined types
- User-defined types must be data types. Using a net type (e.g. wire) is
a syntax error.
- User-defined types without a net type are always variables (i.e.
logic).
- Nets and variables can now be explicitly declared using user-defined
types:
typedef logic [1:0] W;
wire W w;
typedef logic [1:0] V;
var V v;
Fixes #2846
Diffstat (limited to 'passes')
0 files changed, 0 insertions, 0 deletions