diff options
| author | whitequark <whitequark@whitequark.org> | 2020-06-03 14:35:27 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-04 00:02:12 +0000 |
| commit | 9338ff66b9fb86f3485f060b04f4e4b8a1fc18f6 (patch) | |
| tree | c3ef5451736051cfb441f801168944449ce940aa /passes | |
| parent | ebbbe2156e9c5f2d04964840974c915ba8500159 (diff) | |
| download | yosys-9338ff66b9fb86f3485f060b04f4e4b8a1fc18f6.tar.gz yosys-9338ff66b9fb86f3485f060b04f4e4b8a1fc18f6.tar.bz2 yosys-9338ff66b9fb86f3485f060b04f4e4b8a1fc18f6.zip | |
RTLIL: factor out RTLIL::Module::addMemory. NFC.
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/flatten.cc | 8 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 8 |
2 files changed, 2 insertions, 14 deletions
diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 605759bec..dbea12dca 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -79,15 +79,9 @@ struct FlattenWorker for (auto &it : tpl->memories) { IdString m_name = it.first; apply_prefix(cell->name, m_name); - RTLIL::Memory *m = new RTLIL::Memory; - m->name = m_name; - m->width = it.second->width; - m->start_offset = it.second->start_offset; - m->size = it.second->size; - m->attributes = it.second->attributes; + RTLIL::Memory *m = module->addMemory(m_name, it.second); if (m->attributes.count(ID::src)) m->add_strpool_attribute(ID::src, extra_src_attrs); - module->memories[m->name] = m; memory_renames[it.first] = m->name; design->select(module, m); } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 9c0402e0f..535db9465 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -174,15 +174,9 @@ struct TechmapWorker for (auto &it : tpl->memories) { IdString m_name = it.first; apply_prefix(cell->name, m_name); - RTLIL::Memory *m = new RTLIL::Memory; - m->name = m_name; - m->width = it.second->width; - m->start_offset = it.second->start_offset; - m->size = it.second->size; - m->attributes = it.second->attributes; + RTLIL::Memory *m = module->addMemory(m_name, it.second); if (m->attributes.count(ID::src)) m->add_strpool_attribute(ID::src, extra_src_attrs); - module->memories[m->name] = m; memory_renames[it.first] = m->name; design->select(module, m); } |