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author | Aman Goel <amangoel@umich.edu> | 2018-05-13 16:53:35 -0400 |
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committer | Aman Goel <amangoel@umich.edu> | 2018-05-13 16:53:35 -0400 |
commit | 9286acb6870876f27771c039704ded7d9ffef3a9 (patch) | |
tree | 5f7d69f33e55ef94e66c688fad168eafcdec728b /passes | |
parent | 0fad1570b5ab07aabf212242039921c63d1db32a (diff) | |
download | yosys-9286acb6870876f27771c039704ded7d9ffef3a9.tar.gz yosys-9286acb6870876f27771c039704ded7d9ffef3a9.tar.bz2 yosys-9286acb6870876f27771c039704ded7d9ffef3a9.zip |
Add option -expose to setundef pass
Option -expose converts undriven wires to inputs.
Example usage: setundef -undriven -expose [selection]
Diffstat (limited to 'passes')
-rw-r--r-- | passes/cmds/setundef.cc | 32 |
1 files changed, 26 insertions, 6 deletions
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index c11ddbdc1..172b1c3f8 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -81,6 +81,9 @@ struct SetundefPass : public Pass { log(" -undriven\n"); log(" also set undriven nets to constant values\n"); log("\n"); + log(" -expose\n"); + log(" also expose undriven nets as inputs\n"); + log("\n"); log(" -zero\n"); log(" replace with bits cleared (0)\n"); log("\n"); @@ -105,6 +108,7 @@ struct SetundefPass : public Pass { { bool got_value = false; bool undriven_mode = false; + bool expose_mode = false; bool init_mode = false; SetundefWorker worker; @@ -117,6 +121,11 @@ struct SetundefPass : public Pass { undriven_mode = true; continue; } + if (args[argidx] == "-expose") { + got_value = true; + expose_mode = true; + continue; + } if (args[argidx] == "-zero") { got_value = true; worker.next_bit_mode = 0; @@ -157,6 +166,8 @@ struct SetundefPass : public Pass { } extra_args(args, argidx, design); + if (expose_mode && !undriven_mode) + log_cmd_error("Option -expose must be used with option -undriven.\n"); if (!got_value) log_cmd_error("One of the options -zero, -one, -anyseq, or -random <seed> must be specified.\n"); @@ -184,12 +195,21 @@ struct SetundefPass : public Pass { undriven_signals.del(sigmap(conn.second)); RTLIL::SigSpec sig = undriven_signals.export_all(); - for (auto &c : sig.chunks()) { - RTLIL::SigSpec bits; - for (int i = 0; i < c.width; i++) - bits.append(worker.next_bit()); - module->connect(RTLIL::SigSig(c, bits)); - } + if (expose_mode) { + for (auto &c : sig.chunks()) { + c.wire->port_input = true; + log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(c.wire->name)); + } + module->fixup_ports(); + } + else { + for (auto &c : sig.chunks()) { + RTLIL::SigSpec bits; + for (int i = 0; i < c.width; i++) + bits.append(worker.next_bit()); + module->connect(RTLIL::SigSig(c, bits)); + } + } } if (init_mode) |