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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-16 17:51:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-16 17:51:17 +0100 |
| commit | 8ce8a230f458d09f1847ba87a3073cf4c07579d3 (patch) | |
| tree | aa9d82463cef09777d0911953b7cb5f31da9ad3c /passes | |
| parent | 3ed4e34380036c63d6177f41f43767b41201e4a8 (diff) | |
| download | yosys-8ce8a230f458d09f1847ba87a3073cf4c07579d3.tar.gz yosys-8ce8a230f458d09f1847ba87a3073cf4c07579d3.tar.bz2 yosys-8ce8a230f458d09f1847ba87a3073cf4c07579d3.zip | |
Bugfix in dff2dffe
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/dff2dffe.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 339007156..17549bd06 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -173,7 +173,7 @@ struct Dff2dffeWorker return or_input; RTLIL::SigSpec y = module->addWire(NEW_ID); - RTLIL::Cell *c = module->addReduceOr(NEW_ID, or_input, y); + RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y); if (make_gates) { simplemap(module, c); |