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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 12:29:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 12:29:35 -0700 |
| commit | 8684b58bed2875ab67e9b12912d791f9d588f272 (patch) | |
| tree | e66d456aec1ffe83827ac7cb589bdbf1275cf67e /passes | |
| parent | f6203e6bd65f7383f14a15e926fc4b8f5f9a3edf (diff) | |
| parent | a274b7cc86d4f64541d3d2903b4eeed4616ab1d8 (diff) | |
| download | yosys-8684b58bed2875ab67e9b12912d791f9d588f272.tar.gz yosys-8684b58bed2875ab67e9b12912d791f9d588f272.tar.bz2 yosys-8684b58bed2875ab67e9b12912d791f9d588f272.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/equiv/equiv_opt.cc | 5 | ||||
| -rw-r--r-- | passes/sat/async2sync.cc | 1 | ||||
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
3 files changed, 6 insertions, 2 deletions
diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index d4c7f7953..4ab5b1a3e 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -32,7 +32,8 @@ struct EquivOptPass:public ScriptPass log("\n"); log(" equiv_opt [options] [command]\n"); log("\n"); - log("This command checks circuit equivalence before and after an optimization pass.\n"); + log("This command uses temporal induction to check circuit equivalence before and\n"); + log("after an optimization pass.\n"); log("\n"); log(" -run <from_label>:<to_label>\n"); log(" only run the commands between the labels (see below). an empty\n"); @@ -156,6 +157,8 @@ struct EquivOptPass:public ScriptPass if (check_label("prove")) { if (multiclock || help_mode) run("clk2fflogic", "(only with -multiclock)"); + if (!multiclock || help_mode) + run("async2sync", "(only without -multiclock)"); run("equiv_make gold gate equiv"); if (help_mode) run("equiv_induct [-undef] equiv"); diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index 24ae6e448..740248545 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -198,6 +198,7 @@ struct Async2syncPass : public Pass { module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q); } + cell->setPort("\\D", sig_q); cell->setPort("\\Q", new_q); cell->unsetPort("\\EN"); cell->unsetParam("\\EN_POLARITY"); diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 1847186bf..0276283a5 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -417,7 +417,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig"); - ifs.open(buffer); + ifs.open(buffer, std::ifstream::binary); if (ifs.fail()) log_error("Can't open ABC output file `%s'.\n", buffer.c_str()); |