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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:21:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:21:14 -0700 |
| commit | 7959e9d6b25d7afefded4b14e14ccf2b0b5af553 (patch) | |
| tree | 000580f4fe0ce2f3109b65534f6947c92c420681 /passes | |
| parent | 7a45cd58566310f623bd567a393beb8a734ebf60 (diff) | |
| download | yosys-7959e9d6b25d7afefded4b14e14ccf2b0b5af553.tar.gz yosys-7959e9d6b25d7afefded4b14e14ccf2b0b5af553.tar.bz2 yosys-7959e9d6b25d7afefded4b14e14ccf2b0b5af553.zip | |
Fix merge issues
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 4 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 8 |
2 files changed, 2 insertions, 10 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 87235f1a7..0dbe70a68 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -459,7 +459,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip dict<IdString, bool> abc9_box; vector<RTLIL::Cell*> boxes; for (auto cell : module->selected_cells()) { - if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC_FF_))) { + if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) { module->remove(cell); continue; } @@ -533,7 +533,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip cell_stats[mapped_cell->type]++; RTLIL::Cell *existing_cell = nullptr; - if (mapped_cell->type.in(ID($lut), ID($__ABC_FF_))) { + if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) { if (mapped_cell->type == ID($lut) && GetSize(mapped_cell->getPort(ID::A)) == 1 && mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index a07a2f280..0c57733d4 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -256,14 +256,6 @@ struct TechmapWorker if (w->attributes.count(ID(src))) w->add_strpool_attribute(ID(src), extra_src_attrs); } - - - if (it.second->name.begins_with("\\_TECHMAP_REPLACE_")) { - IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_")); - Wire *replace_w = module->addWire(replace_name, it.second); - module->connect(replace_w, w); - } - design->select(module, w); if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) { |