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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-30 20:57:35 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-30 20:57:35 +0200 |
| commit | 77b15dd8e9262f5db6a8154f7ad75a2540e58c60 (patch) | |
| tree | 2076c53f1387bd09b902b6019892c2603d9ee369 /passes | |
| parent | 817ae04ee0c445efaf83e9847d4956f2dae0d857 (diff) | |
| download | yosys-77b15dd8e9262f5db6a8154f7ad75a2540e58c60.tar.gz yosys-77b15dd8e9262f5db6a8154f7ad75a2540e58c60.tar.bz2 yosys-77b15dd8e9262f5db6a8154f7ad75a2540e58c60.zip | |
opt_merge: use the master FF type list
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_merge.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index a95aa74c1..f03faa9cf 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -298,9 +298,7 @@ struct OptMergeWorker module->connect(RTLIL::SigSig(it.second, other_sig)); assign_map.add(it.second, other_sig); - if (it.first == ID::Q && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || - cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") || - cell->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) { + if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell->type)) { for (auto c : it.second.chunks()) { auto jt = c.wire->attributes.find(ID::init); if (jt == c.wire->attributes.end()) |