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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-12 17:42:57 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-12 17:42:57 +0100 |
| commit | 76c4ee096bba99f787dd042bd9a6e988cf72f2dc (patch) | |
| tree | 2a50ba861a2c273bfd01a160758a53f079c38ac1 /passes | |
| parent | 828303791b5f4a50a52d4749be42caac9819bf2a (diff) | |
| download | yosys-76c4ee096bba99f787dd042bd9a6e988cf72f2dc.tar.gz yosys-76c4ee096bba99f787dd042bd9a6e988cf72f2dc.tar.bz2 yosys-76c4ee096bba99f787dd042bd9a6e988cf72f2dc.zip | |
Do not eagerly fix port widths on parameterized cells
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 4786aacaf..037fdb3b2 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -625,6 +625,9 @@ struct HierarchyPass : public Pass { for (auto module : design->modules()) for (auto cell : module->cells()) { + if (GetSize(cell->parameters) != 0) + continue; + Module *m = design->module(cell->type); if (m == nullptr) |