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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-02-22 06:29:11 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-02-22 06:29:11 +0000 |
| commit | 750e7a9a541676f64fc9def64e669f94fa074d28 (patch) | |
| tree | 620d64ec90ff9e887b894a26be1b5afc2b49d409 /passes | |
| parent | 760096e8d2e9e2431bd5f97034bbd4ba01326649 (diff) | |
| download | yosys-750e7a9a541676f64fc9def64e669f94fa074d28.tar.gz yosys-750e7a9a541676f64fc9def64e669f94fa074d28.tar.bz2 yosys-750e7a9a541676f64fc9def64e669f94fa074d28.zip | |
Closes #1714. Fix make failure when NDEBUG=1.
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 8f5718411..54605f90e 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -752,13 +752,11 @@ void reintegrate(RTLIL::Module *module) continue; } -#ifndef NDEBUG RTLIL::Module* box_module = design->module(existing_cell->type); IdString derived_type = box_module->derive(design, existing_cell->parameters); RTLIL::Module* derived_module = design->module(derived_type); log_assert(derived_module); log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int())); -#endif mapped_cell->type = existing_cell->type; RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type); |