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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-04-01 15:02:12 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-04-01 15:02:12 -0700 |
| commit | 73b87e780798fe2c7958b75e4dfddc0dc2169d20 (patch) | |
| tree | db971b48ddb4a763a77e73f96657babf48a35fac /passes | |
| parent | 22035c20ff071ec5c30990258850ecf97de5d5b3 (diff) | |
| download | yosys-73b87e780798fe2c7958b75e4dfddc0dc2169d20.tar.gz yosys-73b87e780798fe2c7958b75e4dfddc0dc2169d20.tar.bz2 yosys-73b87e780798fe2c7958b75e4dfddc0dc2169d20.zip | |
Refine memory support to deal with general Verilog memory definitions.
Diffstat (limited to 'passes')
0 files changed, 0 insertions, 0 deletions