diff options
| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-16 13:21:11 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-16 13:21:11 +0200 |
| commit | 72eacdb9f80e24aa2182dbf567d6fcbe2a5bfaba (patch) | |
| tree | c370ca0f6cb0766520c773a255f985741f3294aa /passes | |
| parent | bb79e050a594fe09b975cecd7a1bdf917b208faa (diff) | |
| download | yosys-72eacdb9f80e24aa2182dbf567d6fcbe2a5bfaba.tar.gz yosys-72eacdb9f80e24aa2182dbf567d6fcbe2a5bfaba.tar.bz2 yosys-72eacdb9f80e24aa2182dbf567d6fcbe2a5bfaba.zip | |
Regression in abc9
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 752535f34..c3c8f879f 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -628,7 +628,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; continue; } - cell_stats[RTLIL::unescape_id(c->type)]++; + cell_stats[c->type]++; RTLIL::Cell *existing_cell = nullptr; if (c->type == ID($lut)) { |