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| author | Clifford Wolf <clifford@clifford.at> | 2019-11-22 15:32:29 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-22 15:32:29 +0100 |
| commit | 72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d (patch) | |
| tree | b499121c6a6f5bd269c871ba08d52656784e03c9 /passes | |
| parent | e110df9c484d5c87429c55da1c1d83fd509a78b3 (diff) | |
| parent | b60f32c6ecc27e0fa1f81a1055cfd1105ed647bd (diff) | |
| download | yosys-72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d.tar.gz yosys-72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d.tar.bz2 yosys-72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d.zip | |
Merge pull request #1511 from YosysHQ/dave/always
sv: Error checking for always_comb, always_latch and always_ff
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/proc/proc_dlatch.cc | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index d9d5dfbed..a0c8351b6 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -349,6 +349,10 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) continue; } + if (proc->get_bool_attribute(ID(always_ff))) + log_error("Found non edge/level sensitive event in always_ff process `%s.%s'.\n", + db.module->name.c_str(), proc->name.c_str()); + for (auto ss : sr->actions) { db.sigmap.apply(ss.first); @@ -383,8 +387,12 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) int offset = 0; for (auto chunk : nolatches_bits.first.chunks()) { SigSpec lhs = chunk, rhs = nolatches_bits.second.extract(offset, chunk.width); - log("No latch inferred for signal `%s.%s' from process `%s.%s'.\n", - db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); + if (proc->get_bool_attribute(ID(always_latch))) + log_error("No latch inferred for signal `%s.%s' from always_latch process `%s.%s'.\n", + db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); + else + log("No latch inferred for signal `%s.%s' from process `%s.%s'.\n", + db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); db.module->connect(lhs, rhs); offset += chunk.width; } @@ -410,8 +418,12 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) cell->set_src_attribute(src); db.generated_dlatches.insert(cell); - log("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n", - db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), log_id(cell)); + if (proc->get_bool_attribute(ID(always_comb))) + log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n", + db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); + else + log("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n", + db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), log_id(cell)); } offset += width; |