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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 11:52:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 11:52:24 -0700 |
| commit | 6e8fda8bf074ca14c5bd58c0dbafc3a5c8ec8e7f (patch) | |
| tree | edad05cc9930d696fd55e74c813a7fcb165d0d24 /passes | |
| parent | cabadb85e2520bd07fa5071d553235da3614b462 (diff) | |
| download | yosys-6e8fda8bf074ca14c5bd58c0dbafc3a5c8ec8e7f.tar.gz yosys-6e8fda8bf074ca14c5bd58c0dbafc3a5c8ec8e7f.tar.bz2 yosys-6e8fda8bf074ca14c5bd58c0dbafc3a5c8ec8e7f.zip | |
Add doc
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_srl.cc | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 45a78a320..22fb93e18 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -168,7 +168,20 @@ struct XilinxSrlPass : public Pass { log("\n"); log(" xilinx_srl [options] [selection]\n"); log("\n"); - log("TODO.\n"); + log("This pass converts chains of built-in flops ($_DFF_[NP]_, $_DFFE_*) as well as\n"); + log("Xilinx flops (FDRE, FDRE_1) into a $__XILINX_SHREG cell. Chains must be of the\n"); + log("same type, clock, clock polarity, enable, enable polarity (when relevant).\n"); + log("Flops with resets cannot be mapped to Xilinx devices and will not be inferred."); + log("\n"); + log(" -minlen N\n"); + log(" min length of shift register (default = 3)\n"); + log("\n"); + log(" -fixed\n"); + log(" infer fixed-length shift registers.\n"); + log("\n"); + log(" -variable\n"); + log(" infer variable-length shift registers (i.e. fixed-length shifts where\n"); + log(" each element also fans-out to a $shiftx cell.\n"); log("\n"); } |