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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-18 11:02:28 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 6bb3d9f9c09993960a5a91fa51f163a7e67e2503 (patch) | |
| tree | 4e06827d7dfa711a2a5d1cd4702d5a0dfb4dddd5 /passes | |
| parent | 9dcf204dece518a48192a90ea962a9d630283e11 (diff) | |
| download | yosys-6bb3d9f9c09993960a5a91fa51f163a7e67e2503.tar.gz yosys-6bb3d9f9c09993960a5a91fa51f163a7e67e2503.tar.bz2 yosys-6bb3d9f9c09993960a5a91fa51f163a7e67e2503.zip | |
Make TimingInfo::TimingInfo(SigBit) constructor explicit
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index e5de2bcc4..e46ad0a02 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -440,7 +440,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) SigSpec O = module->addWire(NEW_ID, GetSize(conn.second)); for (int i = 0; i < GetSize(conn.second); i++) { - auto d = t.at(SigBit(port_wire,i), 0); + auto d = t.at(TimingInfo::NameBit(conn.first,i), 0); if (d == 0) continue; @@ -582,7 +582,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode) else ss << " "; log_assert(GetSize(wire) == 1); - auto it = t.find(SigBit(wire,0)); + auto it = t.find(TimingInfo::NameBit(port_name,0)); if (it == t.end()) // Assume that no setup time means zero ss << 0; @@ -680,7 +680,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode) first = false; else ss << " "; - auto jt = t.find(std::make_pair(i,o)); + auto jt = t.find(std::make_pair(TimingInfo::NameBit(i),TimingInfo::NameBit(o))); if (jt == t.end()) ss << "-"; else |