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| author | David Shah <dave@ds0.me> | 2019-04-02 19:47:50 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-04-02 19:47:50 +0100 |
| commit | 6acbc016f43b1464e6322b895f16d01ed51eea18 (patch) | |
| tree | 1e59344b103e3abd6733824306a6790596c78cd4 /passes | |
| parent | aaa2690a56a5b8210c163c0c63d95f9577038b2d (diff) | |
| download | yosys-6acbc016f43b1464e6322b895f16d01ed51eea18.tar.gz yosys-6acbc016f43b1464e6322b895f16d01ed51eea18.tar.bz2 yosys-6acbc016f43b1464e6322b895f16d01ed51eea18.zip | |
memory_bram: Consider read enable for address expansion register
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/memory/memory_bram.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 85ed1c053..804aa21f9 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -957,6 +957,8 @@ grow_read_ports:; SigSpec addr_ok_q = addr_ok; if ((pi.clocks || pi.make_outreg) && !addr_ok.empty()) { addr_ok_q = module->addWire(NEW_ID); + if (!pi.sig_en.empty()) + addr_ok = module->Mux(NEW_ID, addr_ok_q, addr_ok, pi.sig_en); module->addDff(NEW_ID, pi.sig_clock, addr_ok, addr_ok_q, pi.effective_clkpol); } |