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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-14 13:26:00 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 683c5ce9409b578df518df829b76777ab69cf87b (patch) | |
| tree | 77e3daa3fe6001342fb8667f5962ebff8711bf59 /passes | |
| parent | 1ef1ca812bd057fe0404893e357c10361225e393 (diff) | |
| download | yosys-683c5ce9409b578df518df829b76777ab69cf87b.tar.gz yosys-683c5ce9409b578df518df829b76777ab69cf87b.tar.bz2 yosys-683c5ce9409b578df518df829b76777ab69cf87b.zip | |
abc9_ops: demote lack of box timing info to warning
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index dad39828a..fc2f52157 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -669,8 +669,10 @@ void prep_box(RTLIL::Design *design, bool dff_mode) ss << std::endl; auto &t = timing.setup_module(module).comb; - if (t.empty()) - log_error("(* abc9_box *) module '%s' has no timing information.\n", log_id(module)); + if (t.empty()) { + log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module)); + continue; + } for (const auto &o : outputs) { first = true; |