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| author | Clifford Wolf <clifford@clifford.at> | 2014-05-29 10:26:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-05-29 10:26:55 +0200 |
| commit | 61883b30f3ea0cd22d08519bc93c73f6e193bd65 (patch) | |
| tree | c513abc708a19889f561d5df2875b6bd53e92fd9 /passes | |
| parent | 68c059565a3b75808e74eb481f14cb7f0c907f37 (diff) | |
| parent | 278085fa01a9013051fbec842314cb6b5642e9bb (diff) | |
| download | yosys-61883b30f3ea0cd22d08519bc93c73f6e193bd65.tar.gz yosys-61883b30f3ea0cd22d08519bc93c73f6e193bd65.tar.bz2 yosys-61883b30f3ea0cd22d08519bc93c73f6e193bd65.zip | |
Merge pull request #36 from hansiglaser/master
Various changes merged
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/expose.cc | 8 | ||||
| -rw-r--r-- | passes/sat/miter.cc | 4 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 6 |
3 files changed, 14 insertions, 4 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 2ac7b35f6..831a43aa5 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -259,6 +259,8 @@ struct ExposePass : public Pass { bool flag_evert_dff = false; std::string sep = "."; + log_header("Executing EXPOSE pass (exposing internal signals as outputs).\n"); + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -629,7 +631,7 @@ struct ExposePass : public Pass { w->port_input = true; add_new_wire(module, w); - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); + log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); RTLIL::SigSpec sig; if (cell->connections.count(p->name) != 0) @@ -654,7 +656,7 @@ struct ExposePass : public Pass { w->port_input = true; add_new_wire(module, w); - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); + log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); if (w->port_input) module->connections.push_back(RTLIL::SigSig(it.second, w)); @@ -667,7 +669,7 @@ struct ExposePass : public Pass { } for (auto &it : delete_cells) { - log("Removing cell: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it)); + log("Removing cell: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it), RTLIL::id2cstr(module->cells.at(it)->type)); delete module->cells.at(it); module->cells.erase(it); } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index db12cb57d..6c8e2ff48 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -28,6 +28,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, bool flag_make_outcmp = false; bool flag_make_assert = false; + log_header("Executing MITER pass (creating miter circuit).\n"); + size_t argidx; for (argidx = 2; argidx < args.size(); argidx++) { @@ -102,6 +104,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str()); } + log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name)); + RTLIL::Module *miter_module = new RTLIL::Module; miter_module->name = miter_name; design->modules[miter_name] = miter_module; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 69ffb9230..4c5a0febc 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -106,8 +106,12 @@ struct TechmapWorker if (tpl->memories.size() != 0) log_error("Technology map yielded memories -> this is not supported.\n"); - if (tpl->processes.size() != 0) + if (tpl->processes.size() != 0) { + log("Technology map yielded processes:\n"); + for (auto &it : tpl->processes) + log(" %s",RTLIL::id2cstr(it.first)); log_error("Technology map yielded processes -> this is not supported.\n"); + } // erase from namespace first for _TECHMAP_REPLACE_ to work module->cells.erase(cell->name); |