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author | Clifford Wolf <clifford@clifford.at> | 2014-10-03 10:04:15 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-10-03 10:04:15 +0200 |
commit | 600c6cb013b6cf872f3b3f01c7d88df2092e84d9 (patch) | |
tree | 067c5e1298aa85849534c427b446814b2f2baec7 /passes | |
parent | 7019bc00e4ebd3c535ff6070bec4af6b7f73336b (diff) | |
download | yosys-600c6cb013b6cf872f3b3f01c7d88df2092e84d9.tar.gz yosys-600c6cb013b6cf872f3b3f01c7d88df2092e84d9.tar.bz2 yosys-600c6cb013b6cf872f3b3f01c7d88df2092e84d9.zip |
remove buffers in opt_clean
Diffstat (limited to 'passes')
-rw-r--r-- | passes/opt/opt_clean.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 0e5ed238f..15bbf54e0 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -293,6 +293,19 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose) if (verbose) log("Finding unused cells or wires in module %s..\n", module->name.c_str()); + std::vector<RTLIL::Cell*> delcells; + for (auto cell : module->cells()) + if (cell->type == "$pos") { + bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + RTLIL::SigSpec a = cell->getPort("\\A"); + RTLIL::SigSpec y = cell->getPort("\\Y"); + a.extend_u0(SIZE(y), is_signed); + module->connect(y, a); + delcells.push_back(cell); + } + for (auto cell : delcells) + module->remove(cell); + rmunused_module_cells(module, verbose); rmunused_module_signals(module, purge_mode, verbose); } |