diff options
author | R. Ou <rqou@robertou.com> | 2020-02-17 00:54:33 -0800 |
---|---|---|
committer | R. Ou <rqou@robertou.com> | 2020-02-17 03:08:52 -0800 |
commit | 5fc180ed2d6da82892c7499392c0c5057c3aeec8 (patch) | |
tree | 0e8cc68ac3d8278f458a63cfeb8fe1e9d8ca03d9 /passes | |
parent | 12fa4a3121e2d55da4f8cf6de4242424ff265e77 (diff) | |
download | yosys-5fc180ed2d6da82892c7499392c0c5057c3aeec8.tar.gz yosys-5fc180ed2d6da82892c7499392c0c5057c3aeec8.tar.bz2 yosys-5fc180ed2d6da82892c7499392c0c5057c3aeec8.zip |
extract_counter: Fix clock enable
Diffstat (limited to 'passes')
-rw-r--r-- | passes/techmap/extract_counter.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index 69fdaf269..d1a0f6dec 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -509,13 +509,15 @@ void counter_worker( cell->setPort(ID(CE), extract.ce); } else + { cell->setParam(ID(HAS_CE), RTLIL::Const(0)); + cell->setPort(ID(CE), RTLIL::Const(1)); + } //Hook up hard-wired ports (for now up/down are not supported), default to no parallel output cell->setParam(ID(HAS_POUT), RTLIL::Const(0)); cell->setParam(ID(RESET_TO_MAX), RTLIL::Const(0)); cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN")); - cell->setPort(ID(CE), RTLIL::Const(1)); cell->setPort(ID(UP), RTLIL::Const(0)); //Hook up any parallel outputs |