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author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 15:17:29 +0200 |
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committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 15:59:41 +0200 |
commit | 5628f5a88fa49c126af0149e302a8292229ab9df (patch) | |
tree | 302ebeeb17d5ad6ca87bb145d885fdeb4c0dd25a /passes | |
parent | 4858721637fc5d6ae6d7e0fb0489e0cec8bb388b (diff) | |
download | yosys-5628f5a88fa49c126af0149e302a8292229ab9df.tar.gz yosys-5628f5a88fa49c126af0149e302a8292229ab9df.tar.bz2 yosys-5628f5a88fa49c126af0149e302a8292229ab9df.zip |
opt_mem_feedback: Respect write port priority.
Diffstat (limited to 'passes')
-rw-r--r-- | passes/opt/opt_mem_feedback.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/passes/opt/opt_mem_feedback.cc b/passes/opt/opt_mem_feedback.cc index 90e5cea9b..8e93c93b9 100644 --- a/passes/opt/opt_mem_feedback.cc +++ b/passes/opt/opt_mem_feedback.cc @@ -237,6 +237,21 @@ struct OptMemFeedbackWorker log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", log_id(module), log_id(mem.memid)); + // If a write port has a feedback path that we're about to bypass, + // but also has priority over some other write port, the feedback + // path is not necessarily a NOP — it may overwrite the other port. + // Emulate this effect by converting the priority to soft logic + // (this will affect the other port's enable signal). + for (auto &it : portbit_conds) + { + int wrport_idx = it.first.first; + auto &port = mem.wr_ports[wrport_idx]; + + for (int i = 0; i < wrport_idx; i++) + if (port.priority_mask[i]) + mem.emulate_priority(i, wrport_idx); + } + for (auto &it : portbit_conds) { int wrport_idx = it.first.first; |