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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-05-02 07:59:07 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-05-02 07:59:07 -0700 |
| commit | 509f729e55458eda0ed7869ad269ec52d1956043 (patch) | |
| tree | d936c93a1bb9c52de452b03690c56d44952be49b /passes | |
| parent | 6c361bb19877db8d2a0b6ef79fb1a747276e7b68 (diff) | |
| parent | 98925f6c4be611434e75f0ccf645a7ef8adcfc63 (diff) | |
| download | yosys-509f729e55458eda0ed7869ad269ec52d1956043.tar.gz yosys-509f729e55458eda0ed7869ad269ec52d1956043.tar.bz2 yosys-509f729e55458eda0ed7869ad269ec52d1956043.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/shregmap.cc | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index a541b33be..75eedfbcc 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -178,7 +178,17 @@ struct ShregmapTechXilinx7 : ShregmapTech // Only map if $shiftx exclusively covers the shift register if (shiftx->type == "$shiftx") { - if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) + if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int()) + return false; + // Due to padding the most significant bits of A may be 1'bx, + // and if so, discount them + if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) { + const SigSpec A = shiftx->getPort("\\A"); + const int A_width = shiftx->getParam("\\A_WIDTH").as_int(); + for (int i = GetSize(taps); i < A_width; ++i) + if (A[i] != RTLIL::Sx) return false; + } + else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) return false; } else if (shiftx->type == "$mux") { |