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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-14 08:53:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 509de98468973838aa3b3ff958084693434c8c83 (patch) | |
| tree | 0cd5d60467a2d8ea12aa0d72e27a74dda9ab961d /passes | |
| parent | b66904e9cdef8cd0e0019f9a1a3a7a13abdcc10c (diff) | |
| download | yosys-509de98468973838aa3b3ff958084693434c8c83.tar.gz yosys-509de98468973838aa3b3ff958084693434c8c83.tar.bz2 yosys-509de98468973838aa3b3ff958084693434c8c83.zip | |
submod: revert accidental change
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/submod.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 1f30a5160..2db7cf26b 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -389,7 +389,7 @@ struct SubmodPass : public Pass { while (did_something) { did_something = false; std::vector<RTLIL::IdString> queued_modules; - for (auto mod : design->selected_modules()) + for (auto mod : design->modules()) if (handled_modules.count(mod->name) == 0 && design->selected_whole_module(mod->name)) queued_modules.push_back(mod->name); for (auto &modname : queued_modules) |