diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-01-06 00:16:44 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-06 00:16:44 +0100 |
| commit | 462b22f44fae71767991bd4eb502d009149b3995 (patch) | |
| tree | 2cd6e77f9d0e377d566c072a6ea0b13dc9a932fc /passes | |
| parent | 9ea2511fe87a9a3a4dd179101f42982ed62e78c0 (diff) | |
| download | yosys-462b22f44fae71767991bd4eb502d009149b3995.tar.gz yosys-462b22f44fae71767991bd4eb502d009149b3995.tar.bz2 yosys-462b22f44fae71767991bd4eb502d009149b3995.zip | |
dict<> ref vs insert bugfix
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_const.cc | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 7f800bde9..2eaba15ce 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -669,8 +669,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->unsetPort("\\B"); cell->unsetPort("\\S"); if (cell->type == "$mux") { - cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; - cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"]; + Const width = cell->parameters["\\WIDTH"]; + cell->parameters["\\A_WIDTH"] = width; + cell->parameters["\\Y_WIDTH"] = width; cell->parameters["\\A_SIGNED"] = 0; cell->parameters.erase("\\WIDTH"); cell->type = "$not"; @@ -686,9 +687,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->setPort("\\A", cell->getPort("\\S")); cell->unsetPort("\\S"); if (cell->type == "$mux") { - cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; - cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"]; - cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"]; + auto width = cell->parameters["\\WIDTH"]; + cell->parameters["\\A_WIDTH"] = width; + cell->parameters["\\B_WIDTH"] = width; + cell->parameters["\\Y_WIDTH"] = width; cell->parameters["\\A_SIGNED"] = 0; cell->parameters["\\B_SIGNED"] = 0; cell->parameters.erase("\\WIDTH"); @@ -705,9 +707,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons cell->setPort("\\B", cell->getPort("\\S")); cell->unsetPort("\\S"); if (cell->type == "$mux") { - cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"]; - cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"]; - cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"]; + auto width = cell->parameters["\\WIDTH"]; + cell->parameters["\\A_WIDTH"] = width; + cell->parameters["\\B_WIDTH"] = width; + cell->parameters["\\Y_WIDTH"] = width; cell->parameters["\\A_SIGNED"] = 0; cell->parameters["\\B_SIGNED"] = 0; cell->parameters.erase("\\WIDTH"); @@ -894,8 +897,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (!swapped_ab) { cell->setPort("\\A", cell->getPort("\\B")); - cell->parameters["\\A_WIDTH"] = cell->parameters["\\B_WIDTH"]; - cell->parameters["\\A_SIGNED"] = cell->parameters["\\B_SIGNED"]; + cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH"); + cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED"); } std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6); |