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| author | Jannis Harder <me@jix.one> | 2022-10-24 16:25:33 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-10-24 16:25:33 +0200 |
| commit | 408fc60c95f88671e0d6c5624a10e147334edb4e (patch) | |
| tree | b07daa89e730a8d8b76152d1b3a6174229452257 /passes | |
| parent | 3a37597e9f3cbcd69a28663933074c24d5c03feb (diff) | |
| parent | c77b7343d0412a009436a57764d907e2ae332da2 (diff) | |
| download | yosys-408fc60c95f88671e0d6c5624a10e147334edb4e.tar.gz yosys-408fc60c95f88671e0d6c5624a10e147334edb4e.tar.bz2 yosys-408fc60c95f88671e0d6c5624a10e147334edb4e.zip | |
Merge pull request #3526 from jix/mux-simlib-eval
Consistent $mux undef handling
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index be0cd470b..9cc0170dc 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1494,7 +1494,7 @@ skip_identity: RTLIL::SigSpec input = assign_map(cell->getPort(ID::S)); RTLIL::SigSpec inA = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec inB = assign_map(cell->getPort(ID::B)); - if (input.is_fully_const()) + if (input.is_fully_const() && (!keepdc || input.is_fully_def())) ACTION_DO(ID::Y, input.as_bool() ? cell->getPort(ID::B) : cell->getPort(ID::A)); else if (inA == inB) ACTION_DO(ID::Y, cell->getPort(ID::A)); |