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| author | clairexen <claire@symbioticeda.com> | 2020-06-30 17:12:51 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-30 17:12:51 +0200 |
| commit | 3fb5b4fd8a04179a95b14384a4fd34e87ef7e8e6 (patch) | |
| tree | 6b88a93f0a92b61366e1caadc79888911de2eda2 /passes | |
| parent | 275cee71f6cc3b824bc2bdf2d13ad9f58768721b (diff) | |
| parent | 48b6d3272c3f6ebf1ee1aab3a8abeb5017519b82 (diff) | |
| download | yosys-3fb5b4fd8a04179a95b14384a4fd34e87ef7e8e6.tar.gz yosys-3fb5b4fd8a04179a95b14384a4fd34e87ef7e8e6.tar.bz2 yosys-3fb5b4fd8a04179a95b14384a4fd34e87ef7e8e6.zip | |
Merge pull request #2199 from YosysHQ/mmicko/sim_memory
sim - error when memrd and memwr detected
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/sim.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 1ab082b09..fb496ff87 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -163,7 +163,10 @@ struct SimInstance mem_database[cell] = mem; } - + if (cell->type.in(ID($memwr),ID($memrd))) + { + log_error("$memrd and $memwr cells have to be merged to stand-alone $mem cells (execute memory_collect pass)\n"); + } if (cell->type.in(ID($assert), ID($cover), ID($assume))) { formal_database.insert(cell); } |