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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-21 19:24:16 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-21 19:24:16 +0100 |
| commit | 3b97b612feb07529abd99f913edb70104d1f259a (patch) | |
| tree | 584e5d3ec44e8c3928a6c9527e2ae2b74f2a2e2e /passes | |
| parent | 0e371109b03b7700b22fedcd96e9508a01f2b662 (diff) | |
| parent | 4c82ddf39412fa7f90d71f259d578f98e732c865 (diff) | |
| download | yosys-3b97b612feb07529abd99f913edb70104d1f259a.tar.gz yosys-3b97b612feb07529abd99f913edb70104d1f259a.tar.bz2 yosys-3b97b612feb07529abd99f913edb70104d1f259a.zip | |
Merge pull request #822 from litghost/expand_setundef
Add -params mode to force undef parameters in selected cells.
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/setundef.cc | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 56ef2d125..aea3165e4 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -143,6 +143,9 @@ struct SetundefPass : public Pass { log(" -init\n"); log(" also create/update init values for flip-flops\n"); log("\n"); + log(" -params\n"); + log(" replace undef in cell parameters\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { @@ -150,6 +153,7 @@ struct SetundefPass : public Pass { bool undriven_mode = false; bool expose_mode = false; bool init_mode = false; + bool params_mode = false; SetundefWorker worker; log_header(design, "Executing SETUNDEF pass (replace undef values with defined constants).\n"); @@ -199,6 +203,10 @@ struct SetundefPass : public Pass { init_mode = true; continue; } + if (args[argidx] == "-params") { + params_mode = true; + continue; + } if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) { got_value = true; worker.next_bit_mode = MODE_RANDOM; @@ -228,6 +236,27 @@ struct SetundefPass : public Pass { for (auto module : design->selected_modules()) { + if (params_mode) + { + for (auto *cell : module->cells()) + { + // Only modify selected cells. + if (!design->selected(module, it)) { + continue; + } + + for (auto ¶meter : cell->parameters) + { + for (auto &bit : parameter.second.bits) { + if (bit > RTLIL::State::S1) + { + bit = worker.next_bit(); + } + } + } + } + } + if (undriven_mode) { if (!module->processes.empty()) |