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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-23 14:38:48 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-03-23 14:38:48 +0100 |
| commit | 3b796c033cc40a753e24f21b25b2701a30f022f1 (patch) | |
| tree | 237d5e489e8c996061cfaed1e716a704cb9a08b7 /passes | |
| parent | a440f82586eda461ae2a90cba7a14d7078c41f37 (diff) | |
| download | yosys-3b796c033cc40a753e24f21b25b2701a30f022f1.tar.gz yosys-3b796c033cc40a753e24f21b25b2701a30f022f1.tar.bz2 yosys-3b796c033cc40a753e24f21b25b2701a30f022f1.zip | |
Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes')
0 files changed, 0 insertions, 0 deletions