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| author | Clifford Wolf <clifford@clifford.at> | 2014-10-11 11:42:08 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-11 11:42:08 +0200 |
| commit | 35fbc0b35fb2dafa1b7d1df98ed72688e2eeead6 (patch) | |
| tree | bbeb61f87150444f2587225518eaa82c8704eef0 /passes | |
| parent | 8263f6a74a822579f3c1da7d8b128ea8ab7b4d79 (diff) | |
| download | yosys-35fbc0b35fb2dafa1b7d1df98ed72688e2eeead6.tar.gz yosys-35fbc0b35fb2dafa1b7d1df98ed72688e2eeead6.tar.bz2 yosys-35fbc0b35fb2dafa1b7d1df98ed72688e2eeead6.zip | |
Do not the 'z' modifier in format string (another win32 fix)
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/fsm/fsm_expand.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_recode.cc | 6 | ||||
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 | ||||
| -rw-r--r-- | passes/opt/opt_muxtree.cc | 4 |
4 files changed, 7 insertions, 7 deletions
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index ecd4bf762..a261eb22b 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -239,7 +239,7 @@ struct FsmExpand if (merged_set.size() > 0 && !already_optimized) FsmData::optimize_fsm(fsm_cell, module); - log(" merged %zd cells into FSM.\n", merged_set.size()); + log(" merged %d cells into FSM.\n", GetSize(merged_set)); } }; diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 2b9a26d44..06ac58f0f 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -41,9 +41,9 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData & prefix, RTLIL::unescape_id(module->name).c_str()); fprintf(f, "set_fsm_encoding {"); - for (size_t i = 0; i < fsm_data.state_table.size(); i++) { - fprintf(f, " s%zd=2#", i); - for (int j = int(fsm_data.state_table[i].bits.size())-1; j >= 0; j--) + for (int i = 0; i < GetSize(fsm_data.state_table); i++) { + fprintf(f, " s%d=2#", i); + for (int j = GetSize(fsm_data.state_table[i].bits)-1; j >= 0; j--) fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0'); } fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 87d115027..4b414d3cb 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -281,7 +281,7 @@ void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, bool f delete mod; } - log("Removed %zd unused modules.\n", del_modules.size()); + log("Removed %d unused modules.\n", GetSize(del_modules)); } bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 88ae43f0e..7bdc54afa 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -174,12 +174,12 @@ struct OptMuxtreeWorker for (auto &mi : mux2info) { std::vector<int> live_ports; - for (size_t port_idx = 0; port_idx < mi.ports.size(); port_idx++) { + for (int port_idx = 0; port_idx < GetSize(mi.ports); port_idx++) { portinfo_t &pi = mi.ports[port_idx]; if (pi.enabled) { live_ports.push_back(port_idx); } else { - log(" dead port %zd/%zd on %s %s.\n", port_idx+1, mi.ports.size(), + log(" dead port %d/%d on %s %s.\n", port_idx+1, GetSize(mi.ports), mi.cell->type.c_str(), mi.cell->name.c_str()); removed_count++; } |