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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-15 10:29:25 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-15 10:29:25 +0100 |
| commit | 35b4a2c553557b7b012edabf1bab805c74bd7892 (patch) | |
| tree | 8bd3cfacb738dab8e6b080b99328020138392b16 /passes | |
| parent | cd5767d61ba31e8990db0913b6a08f2563c49565 (diff) | |
| download | yosys-35b4a2c553557b7b012edabf1bab805c74bd7892.tar.gz yosys-35b4a2c553557b7b012edabf1bab805c74bd7892.tar.bz2 yosys-35b4a2c553557b7b012edabf1bab805c74bd7892.zip | |
Fixed gcc warnings and added error handling to shell escape
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/scc/scc.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/scc/scc.cc b/passes/scc/scc.cc index e665fd09e..0dde3cbe8 100644 --- a/passes/scc/scc.cc +++ b/passes/scc/scc.cc @@ -73,6 +73,7 @@ struct SccWorker } if (cellLabels[cell].first == cellLabels[cell].second) + { if (cellStack.back() == cell) { cellStack.pop_back(); @@ -93,6 +94,7 @@ struct SccWorker sccList.push_back(scc); log("\n"); } + } } SccWorker(RTLIL::Design *design, RTLIL::Module *module, bool allCellTypes, int maxDepth) : design(design), module(module), sigmap(module) |