diff options
| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-20 16:30:30 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-20 16:30:30 -0800 |
| commit | 32853b1f8d8cefff36bf5852a04cdaef1bcb2035 (patch) | |
| tree | 8a685fdd3abd597a72ec52d2d9b8b55ce26d9df4 /passes | |
| parent | 869343b040d60ffa9bfdda81660c2ecd88848e79 (diff) | |
| download | yosys-32853b1f8d8cefff36bf5852a04cdaef1bcb2035.tar.gz yosys-32853b1f8d8cefff36bf5852a04cdaef1bcb2035.tar.bz2 yosys-32853b1f8d8cefff36bf5852a04cdaef1bcb2035.zip | |
lut/not/and suffix to be ${lut,not,and}
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index cc906bae7..96f55d5d3 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -592,7 +592,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (a_bit.wire->port_input) { // If it's a NOT gate that comes from a primary input directly // then implement it using a LUT - cell = module->addLut(remap_name(stringf("%slut", c->name.c_str())), + cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())), RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset), RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset), 1); @@ -603,9 +603,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // (TODO: Optimise by not cloning unless will increase depth) RTLIL::IdString driver_name; if (GetSize(a_bit.wire) == 1) - driver_name = stringf("%slut", a_bit.wire->name.c_str()); + driver_name = stringf("%s$lut", a_bit.wire->name.c_str()); else - driver_name = stringf("%s[%d]lut", a_bit.wire->name.c_str(), a_bit.offset); + driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset); RTLIL::Cell* driver = mapped_mod->cell(driver_name); log_assert(driver); auto driver_a = driver->getPort("\\A").chunks(); @@ -616,7 +616,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (b == RTLIL::State::S0) b = RTLIL::State::S1; else if (b == RTLIL::State::S1) b = RTLIL::State::S0; } - cell = module->addLut(remap_name(stringf("%slut", c->name.c_str())), + cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())), driver_a, RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset), driver_lut); |