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author | Clifford Wolf <clifford@clifford.at> | 2014-09-30 19:16:40 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-09-30 19:16:40 +0200 |
commit | 2ee03f5da42e03cc2e5e17b8394ed4f0d24cf21b (patch) | |
tree | 040e136e1484f9f46e4ab2b623fcd1fd3fce1e32 /passes | |
parent | 0b8cfbc6fde8e7500c5df38c74e1da2d74e588bd (diff) | |
download | yosys-2ee03f5da42e03cc2e5e17b8394ed4f0d24cf21b.tar.gz yosys-2ee03f5da42e03cc2e5e17b8394ed4f0d24cf21b.tar.bz2 yosys-2ee03f5da42e03cc2e5e17b8394ed4f0d24cf21b.zip |
set "keep" on modules with $assert cells in "hierarchy"
Diffstat (limited to 'passes')
-rw-r--r-- | passes/hierarchy/hierarchy.cc | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 2c77a892a..960fc1929 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -286,6 +286,17 @@ void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, bool f log("Removed %zd unused modules.\n", del_modules.size()); } +bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) +{ + if (cache.count(mod) == 0) + for (auto c : mod->cells()) { + RTLIL::Module *m = mod->design->module(c->type); + if ((m != nullptr && set_keep_assert(cache, m)) || c->type == "$assert") + return cache[mod] = true; + } + return cache[mod]; +} + struct HierarchyPass : public Pass { HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { } virtual void help() @@ -317,6 +328,11 @@ struct HierarchyPass : public Pass { log(" per default this pass also converts positional arguments in cells\n"); log(" to arguments using port names. this option disables this behavior.\n"); log("\n"); + log(" -nokeep_asserts\n"); + log(" per default this pass sets the \"keep\" attribute on all modules\n"); + log(" that directly or indirectly contain one or more $assert cells. this\n"); + log(" option disables this behavior.\n"); + log("\n"); log(" -top <module>\n"); log(" use the specified top module to built a design hierarchy. modules\n"); log(" outside this tree (unused modules) are removed.\n"); @@ -353,6 +369,7 @@ struct HierarchyPass : public Pass { bool generate_mode = false; bool keep_positionals = false; + bool nokeep_asserts = false; std::vector<std::string> generate_cells; std::vector<generate_port_decl_t> generate_ports; @@ -410,6 +427,10 @@ struct HierarchyPass : public Pass { keep_positionals = true; continue; } + if (args[argidx] == "-nokeep_asserts") { + nokeep_asserts = true; + continue; + } if (args[argidx] == "-libdir" && argidx+1 < args.size()) { libdirs.push_back(args[++argidx]); continue; @@ -477,6 +498,15 @@ struct HierarchyPass : public Pass { mod_it.second->attributes.erase("\\top"); } + if (!nokeep_asserts) { + std::map<RTLIL::Module*, bool> cache; + for (auto mod : design->modules()) + if (set_keep_assert(cache, mod)) { + log("Module %s directly or indirectly contains $assert cells -> setting \"keep\" attribute.\n", log_id(mod)); + mod->set_bool_attribute("\\keep"); + } + } + if (!keep_positionals) { std::set<RTLIL::Module*> pos_mods; |