diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-01-24 12:16:46 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-24 12:16:46 +0100 |
| commit | 2a9ad48eb63a5f019c528fe46ceca0065364a44d (patch) | |
| tree | a84eec02de3e555ca502d9fc4cdc2d9ca66b203c /passes | |
| parent | 8fe9ab50e51204e5709eaad0fbf2ffb5397a0194 (diff) | |
| download | yosys-2a9ad48eb63a5f019c528fe46ceca0065364a44d.tar.gz yosys-2a9ad48eb63a5f019c528fe46ceca0065364a44d.tar.bz2 yosys-2a9ad48eb63a5f019c528fe46ceca0065364a44d.zip | |
Added ENABLE_NDEBUG makefile options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/share.cc | 4 | ||||
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 8 | ||||
| -rw-r--r-- | passes/tests/test_abcloop.cc | 4 |
3 files changed, 12 insertions, 4 deletions
diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 7ab50991d..3133cb2a6 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -1061,7 +1061,9 @@ struct ShareWorker ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) : config(config), design(design), module(module), mi(module) { + #ifndef NDEBUG bool before_scc = module_has_scc(); + #endif generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end()); generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end()); @@ -1355,8 +1357,10 @@ struct ShareWorker log_assert(recursion_state.empty()); + #ifndef NDEBUG bool after_scc = before_scc || module_has_scc(); log_assert(before_scc == after_scc); + #endif } }; diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index cc6f97c7e..b0318a0b3 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -365,8 +365,12 @@ static void map_sr_to_arst(const char *from, const char *to) if (!cell_mappings.count(from) || cell_mappings.count(to) > 0) return; - char from_clk_pol = from[8], from_set_pol = from[9], from_clr_pol = from[10]; - char to_clk_pol = to[6], to_rst_pol = to[7], to_rst_val = to[8]; + char from_clk_pol YS_ATTRIBUTE(unused) = from[8]; + char from_set_pol = from[9]; + char from_clr_pol = from[10]; + char to_clk_pol YS_ATTRIBUTE(unused) = to[6]; + char to_rst_pol YS_ATTRIBUTE(unused) = to[7]; + char to_rst_val = to[8]; log_assert(from_clk_pol == to_clk_pol); log_assert(to_rst_pol == from_set_pol && to_rst_pol == from_clr_pol); diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc index 853339b95..753fa7bf2 100644 --- a/passes/tests/test_abcloop.cc +++ b/passes/tests/test_abcloop.cc @@ -132,7 +132,7 @@ static void test_abcloop() SatGen satgen(&ez, &sigmap); for (auto c : module->cells()) { - bool ok = satgen.importCell(c); + bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c); log_assert(ok); } @@ -182,7 +182,7 @@ static void test_abcloop() SatGen satgen(&ez, &sigmap); for (auto c : module->cells()) { - bool ok = satgen.importCell(c); + bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c); log_assert(ok); } |