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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-25 10:31:52 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-25 12:09:57 +0200 |
| commit | 2397078485aca763453e019fd980ced992b0abed (patch) | |
| tree | 2e86d3ea63a638c546489c1ee661cc85d4cdaf89 /passes | |
| parent | 914ae3401eb9c05564391b5f0d3b6fc069f7cbc0 (diff) | |
| download | yosys-2397078485aca763453e019fd980ced992b0abed.tar.gz yosys-2397078485aca763453e019fd980ced992b0abed.tar.bz2 yosys-2397078485aca763453e019fd980ced992b0abed.zip | |
Keep modules with $assume (like $assert)
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index d655af0d7..bfa3890a2 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -315,7 +315,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) if (cache.count(mod) == 0) for (auto c : mod->cells()) { RTLIL::Module *m = mod->design->module(c->type); - if ((m != nullptr && set_keep_assert(cache, m)) || c->type == "$assert") + if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume")) return cache[mod] = true; } return cache[mod]; |