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author | Clifford Wolf <clifford@clifford.at> | 2014-01-19 14:03:40 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-01-19 14:03:40 +0100 |
commit | 1e67099b77904802880ad7c53d2cac33c6df456f (patch) | |
tree | 87deccc08f9e4bbbc7d2448852daf68d4ba0b35e /passes | |
parent | 9a1eb45c7517f224a2516ce235fd53d01d9ef908 (diff) | |
download | yosys-1e67099b77904802880ad7c53d2cac33c6df456f.tar.gz yosys-1e67099b77904802880ad7c53d2cac33c6df456f.tar.bz2 yosys-1e67099b77904802880ad7c53d2cac33c6df456f.zip |
Added $assert cell
Diffstat (limited to 'passes')
-rw-r--r-- | passes/opt/opt_clean.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 2921c92d8..051d8dc68 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -47,7 +47,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) wire2driver.insert(sig, cell); } } - if (cell->type == "$memwr" || cell->get_bool_attribute("\\keep")) + if (cell->type == "$memwr" || cell->type == "$assert" || cell->get_bool_attribute("\\keep")) queue.insert(cell); unused.insert(cell); } |