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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-05 15:52:29 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-05 15:52:29 +0100 |
| commit | 1d34fd7608d4bb9929b9e6ce6eb5038e3d8b3a0a (patch) | |
| tree | 40df3df37aa20b06ea948a4eb1a5793def05c2cd /passes | |
| parent | 27fec4e77c8d116deb90398400f5f2a1eb5cf785 (diff) | |
| download | yosys-1d34fd7608d4bb9929b9e6ce6eb5038e3d8b3a0a.tar.gz yosys-1d34fd7608d4bb9929b9e6ce6eb5038e3d8b3a0a.tar.bz2 yosys-1d34fd7608d4bb9929b9e6ce6eb5038e3d8b3a0a.zip | |
Added support for "keep" attributes on wires
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_clean.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 3d75b6404..8e3691b34 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -190,6 +190,11 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (!wire->port_input) used_signals_nodrivers.add(sig); } + if (wire->get_bool_attribute("\\keep")) { + RTLIL::SigSpec sig = RTLIL::SigSpec(wire); + assign_map.apply(sig); + used_signals.add(sig); + } } std::vector<RTLIL::Wire*> del_wires; |